1. Field of the Invention
The present invention relates to a clock generating circuit.
2. Description of the Related Art
A PLL (Phase Locked Loop) circuit and a DLL (Delay Locked Loop) circuit are generally known as a clock generating circuit that generates a clock synchronized with an input clock. For example, FIG. 13 of Japanese Patent Application Laid-Open Publication No. Hei8-307254 discloses the PLL circuit including a phase comparator, a charge pump, a loop filter, and a voltage-controlled oscillator. For example, FIG. 15 of Japanese Patent Application Laid-Open Publication No. Hei8-307254 discloses the DLL circuit that including a voltage-controlled delay circuit in place of the voltage-controlled oscillator. Such a PLL circuit or DLL circuit compares two clock signals at the phase comparator, converts a result of such comparison into a controlled potential by the charge pump and the loop filter, and controls the voltage-controlled oscillator/voltage-controlled delay circuit so that a frequency difference and a phase difference between the clock signals are reduced based on the controlled potential.
As such, it is possible to generate a clock synchronized with the input clock by using the PLL circuit or the DLL circuit.
In the above PLL circuit or DLL circuit, however, since the clock (hereinafter referred to as sub-clock) generated based on the input signal served as a reference (hereinafter referred to as main clock) is controlled according to the result of comparison with the main clock, when the main clock is stopped, the sub-clock may get out of normal control, causing a problem in operation of a circuit supplied with the sub-clock.
For this reason, attention must be paid to design of a system as a whole needs to be considered so that the sub-clock is generated after the main clock is started and the main clock is stopped after the sub-clock is stopped.